The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching. In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below.
Presented in FIGS. 1A-1G, is a cross sectional depiction of a dual Damascene fabrication process. Referring to FIG. 1A, an example of a typical substrate, 100, used for dual damascene fabrication is illustrated. Substrate 100 includes a pre-formed dielectric layer 103 (such as silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which; a diffusion barrier layer 105 has been deposited followed by inlaying with copper conductive routes 107. Because copper or other mobile conductive material provides the conductive paths of the semiconductor wafer, the underlying silicon devices must be protected from metal ions (e.g., copper) that might otherwise diffuse into the silicon. Suitable materials for diffusion barrier layer 105 include tantalum, tantalum nitride, tungsten, titanium, titanium tungsten, titanium nitride, and the like. In a typical process, barrier layer 105 is formed by a physical vapor deposition (PVD) process such as sputtering or a chemical vapor deposition (CVD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in damascene processes, as depicted in these figures. The resultant partially fabricated integrated circuit 100 is a representative substrate for subsequent Damascene processing, as depicted in FIGS. 1B-1G.
As depicted in FIG. 1B, a silicon nitride or silicon carbide diffusion barrier 109 is deposited to encapsulate conductive routes 107. Next, a first dielectric layer, 111, of a dual damascene dielectric structure is deposited on diffusion barrier 109. This is followed by deposition of an etch-stop layer 113 (typically composed of silicon nitride or silicon carbide) on the first dielectric layer 111.
The process follows, as depicted in FIG. 1C, where a second dielectric layer 115 of the dual damascene dielectric structure is deposited in a similar manner to the first dielectric layer 111, onto etch-stop layer 113. Deposition of an antireflective layer 117, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in FIGS. 1D-1E, with etching of vias and trenches in the first and second dielectric layers. First, vias 119 are etched through antireflective layer 117 and the second dielectric layer 115. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias 119 is controlled such that etch-stop layer 113 is not penetrated. As depicted in FIG. 1E, in a subsequent lithiography process, antireflective layer 117 is removed and trenches 121 are etched in the second dielectric layer 115; vias 119 are propagated through etch-stop layer 113, first dielectric layer 111, and diffusion barrier 109.
Next, as depicted in FIG. 1F, these newly formed vias and trenches are, as described above, coated with a conformal diffusion barrier 123. As mentioned above, barrier 123 comprises tantalum, titanium, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier 123 is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electrofilling of the features with copper inlay. FIG. 1G shows the completed dual Damascene process, wherein copper conductive routes 125 are inlaid (seed layer not depicted) into the via and trench features over barrier layer 123.
Copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated by only by diffusion barrier 123 which is itself somewhat conductive. Although conformal barrier layers are sufficiently conductive for conventional circuitry, with the continuing need for faster (signal propagation speed) and more reliable microchip circuitry, the resistance of conformal barrier layers comprised of the materials mentioned above is problematic. To reduce resistance between the copper routes, a portion of the barrier layer may be etched away in order to expose the lower copper plug. In this way, the subsequent copper inlay can be deposited directly onto the lower copper plug. Conventional methods for etching away barrier layers only at the bottom of vias (for example, the region of barrier layer 123 contacting copper inlay 107 in FIG. 1F) are problematic in that their not selective enough. That is, conventional etch methods remove barrier material from undesired areas as well, such as the corners (edges) of the via, trench, and, field regions. This can destroy critical dimensions of the via and trench features (faceting of the corners) and unnecessarily exposes the dielectric to plasma.
In addition, conventional etching methods do not address unlanded contact regions. As illustrated in FIG. 1F, a portion of barrier layer 123 located at via bottom 127 does not fully contact copper inlay 107. In this case, a portion of the barrier rests on copper inlay 107 and a portion rests on dielectric 103. A conventional barrier layer etch, meant to expose copper inlay 107, would expose both copper inlay 107 and dielectric 103 in region 127. In that case, more process steps would be needed to repair or replace barrier layer on the newly-exposed region of dielectric 103, before any subsequent copper could be deposited thereon. Using conventional unselective xe2x80x9cblanketxe2x80x9d conformal deposition methods to reprotect the dielectric, one would create the same problem that existed before the etch, that is, higher resistance between copper routes due to the barrier layer itself.
What is therefore needed is a way to selectively form barrier layers on integrated circuit structures, such that barrier layer material deposited on exposed dielectric surfaces is conformal and continuous, while barrier material deposited on exposed conductor surfaces is discontinuous. In this way, the resistance between inlayed metal conductive routes is reduced.
The present invention provides methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention feature selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into a diffusion barrier layer having low resistance in the vias.
In a preferred embodiment of the invention, the selective deposition of the metal-nitride barrier material is achieved by controlling process conditions during chemical vapor deposition. This method allows one to take advantage of the differential material properties of conductor and dielectric. In a single deposition, barrier material is deposited on dielectric and conductor regions of a partially fabricated integrated circuit; the morphology of the deposited material is continuous on the dielectric regions and discontinuous on the conductor regions. The discontinuity of the barrier material on the conductor regions allows for lower electrical resistance between the conductor regions and subsequently applied conductive routes.
One aspect of the invention pertains to a method for forming a diffusion barrier layer on a partially fabricated integrated circuit, said circuit containing exposed regions of a dielectric and a conductor. The method comprises depositing a metal-nitride barrier material onto the partially fabricated integrated circuit such that the morphology of the metal-nitride barrier material on the dielectric is continuous and the morphology of the metal-nitride barrier material on the conductor is discontinuous; and converting at least part of the metal-nitride barrier material to a metal silicon nitride to form the diffusion barrier layer. The method is particularly useful in Damascene processing, especially when copper is the metal used for conductive routes.
In a preferred embodiment, TiN is the metal-nitride barrier material. Preferably it is deposited by exposing the partially fabricated integrated circuit to a gas-phase mixture of a tetrakis(dialkylamido) titanium compound and ammonia, while the partially fabricated integrated circuit is heated. A preferred compound for the method is tetrakis(diethylamido) titanium, or TDEAT. Generally, the partially fabricated integrated circuit (wafer) is heated to between about 100 and 400xc2x0 C. and the gas-phase mixture is passed over the wafer at reduced pressure. The flow rates and ratios of the gases in the gas-phase mixture is dependent on the particular method used, as will be discussed in more detail in the detailed description below. The method is performed at pressures in the range of between about 10 and 400 torr, more preferably between about 50 and 70 torr.
Preferably the TiN barrier material deposited on the dielectric is between about 10 xc3x85 and 100 xc3x85 thick, even more preferably about 50 xc3x85 thick. It is most desirable that the TIN barrier material is deposited on the dielectric at a rate of between about 1 and 10 xc3x85 per second.
A preferred way of converting the selectively deposited TiN barrier material to titanium silicon nitride is by exposure of the deposited TiN barrier material to SiH4. More specifically, performing an in-situ exposure of the deposited TiN barrier material to SiH4, preferably while heating the substrate upon which the TiN is deposited. Deposition of the TiN barrier material and the exposure of that material to SiH4 are generally performed in-situ, but this need not be the case.
Aspects of the invention also pertain to an integrated circuit (IC) or a partially fabricated integrated circuit having a barrier layer comprising a metal silicon nitride. The barrier layer will have a continuous morphology over a dielectric upon which it was formed and discontinuous morphology over a conductor upon which it was formed. Preferably, the metal silicon nitride is titanium silicon nitride.
Preferably such an IC is formed by the methods described herein, although this need not be the case. When circuits of the invention contain titanium silicon nitride barrier layers, forming the barrier layer comprises depositing a TiN barrier material over the dielectric and the conductor and converting at least part of the TiN barrier material to titanium silicon nitride. Preferably depositing the TiN barrier material comprises exposing the integrated circuit or partially fabricated integrated circuit to a gas-phase mixture of a tetrakis(dialkylamido) titanium compound and ammonia, while the integrated circuit or partially fabricated integrated circuit is heated. Most preferably, tetrakis(diethylamido) titanium is the organometallic used to form the TiN barrier material and a portion of the TiN barrier material is converted to titanium silicon nitride by exposure to SiH4, under the conditions outlined above.
The integrated circuit or partially fabricated integrated circuits of the invention preferably contain copper for conductive routes with barrier layers formed from TiN barrier material deposited at between about 10 xc3x85 and 100 xc3x85 thick, more preferably about 50 xc3x85 thick.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.